1. Field of the Invention
The present invention relates in general to a programmable clock signal generator which adjusts timing of successive pulses of its output clock signal with a resolution of P seconds, and in particular to a clock signal generator programmed to produce a clock signal having an average period between successive pulses of j*P seconds, where j is a non-integer number, by providing non-uniform intervals between successive clock signal pulses.
2. Description of Related Art
FIG. 1 depicts in block diagram form a prior art clock signal generator 10 for providing an adjustable frequency clock signal MCLK synchronized to a reference clock signal ROSC having period PROSC provided by a stable oscillator 24. Clock signal generator 10 includes a set of gates 14 connected in a closed loop to form a ring oscillator 16. Ring oscillator 16 provides a set of N tap signals T0-TNxe2x88x921 at the outputs of gates 14. In the example illustrated in FIG. 1, N is 5.
The ROSC signal output of counter 17 and tap signal T4 serve as inputs to a conventional phase lock loop (PLL) controller 18. Controller 18 produces a CNTRL signal supplying power to all gates 14 for adjusting the switching speed of the gates. When tap signal T4 lags the ROSC signal, controller 18 sets the CNTRL signal voltage to increase the switching speed of gates 14. When tap signal T4 leads the ROSC signal, controller 18 adjusts the CNTRL signal voltage to decrease the switching speed of gates 14. Thus controller 18 compares signal ROSC to signal T4 and adjusts the switching speed of all gates 14 to phase lock the T4 signal to the ROSC signal.
A multiplexer 20 having five inputs 0-4 produces output signal MCLK. Tap signals T0-T4 drive multiplexer inputs 0-4 through a set of pulse shaping circuits 19. A sequencer 23 produces a control data sequence SW to signal multiplexer 20 to deliver one of its input signals to a gating circuit 21 at its output on each cycle of the ROSC signal. Gating circuit 21 normally passes the output signal of multiplexer 20 as the MCLK output of clock signal generator 10. However, sequencer 23 may also occasionally produce a SKIP signal pulse telling gating circuit 21 to block the output of multiplexer 20 for the next ROSC signal cycle. The SKIP signal also tells another gating circuit 22 to block a next ROSC signal pulse from clocking sequencer 23. A PROG signal tells sequencer 23 precisely what values to assign to the SW data sequence as well as when to assert the SKIP signal. The SW data and SKIP signal sequences control the timing of each pulse of the MCLK clock signal, and thereby control the phase and frequency of the MCLK signal.
FIG. 2 illustrates the timing with respect to the ROSC signal of the various signals IN(0)-IN(4) provided to multiplexer inputs 0-4. The ROSC signal and input signals IN(0)-IN(4) all have the same frequency, and the phase of the IN(4) input signal matches the phase of the ROSC signal. Input signal IN(0) is delayed with respect to the ROSC signal by P, the switching delay of one gate. Each successive signal of the remaining input signals IN(k) is delayed with respect to the ROSC signal by an additional (k+1)*P. Thus, for example, IN(3) is delayed with respect to the ROSC signal by 4P.
FIG. 2 also illustrates examples MCLK(a)-MCLK(d) of output signal MCLK provided in response to four different SW and SKIP signal patterns. Suppose we want an output signal MCLK(a) with the same frequency as ROSC but with a different phase. To do this we program sequencer 23 to set signal SW so that multiplexer 20 selects input signal IN(1) on each cycle of the ROSC signal and never asserts the SKIP signal. Thus, signal SW supplies a sequence of data values to multiplexer 20 of the form SW={1,1,1, . . . }. The resultant signal MCLK(a) is shifted in phase by 2P with respect to the ROSC signal.
Alternatively, when we want clock signal generator 10 to produce an output signal MCLK(b) having a period equal to 1.2PROSC, then we program sequencer 23 to set signal SW to value SW=0 for the first ROSC period and then switch signal SW to value SW=1 at the start of the second ROSC period and so on. Note that because MCLK(b) is of lower frequency than ROSC, the gating circuit 22 must occasionally block a multiplexer output pulse. This occurs, for example, during the fifth ROSC cycle. Thus sequencer 23 asserts the SKIP signal to gating circuits 21 and 22 during the fifth ROSC cycle to tell gating circuit 21 to inhibit the MCLK output of multiplexer 21 and to gating circuit 22 to inhibit sequencer 23 from supplying signal SW to multiplexer 21. Thus, to produce MCLK(b) signal SW is a repetitive sequence SW={0,1,2,3,4} while the skip signal has the form SKIP={0,0,0,0,1}.
When we want clock signal generator 10 to produce an output signal MCLK(c) with a period equal to 1.4PROSC, then we program sequencer 23 to generate a repeating SW signal sequence of the form SW={0,2,4,1,3} with a corresponding SKIP signal of the form SKIP={0,0,1,0,0,0,1}. A set of SW and SKIP data sequences of the form SW={0,0,0, . . . } and SKIP={0,1,0,1, . . . } produces an output signal MCLK(d) with a period twice that of the ROSC signal, or 2PROSC.
Thus clock signal generator 10 can produce a variety of output clock signals MCLK whose frequencies depend on the programming of sequencer 23. However, the resolution P with which clock signal generator 10 can adjust the period of its MCLK output signal is limited to the period PROSC of the ROSC signal divided by the number N of gates 14 in oscillator 16, or PROSC/N. In the example illustrated in FIG. 1, the period resolution of clock signal generator 10 is P=PROSC/5.
By adding more gates 14 to oscillator 16 we can improve the period resolution P of clock signal generator 10, but when N becomes sufficiently high P=PROSC/N falls to a level that is masked by the noise or xe2x80x9cjitterxe2x80x9d in the MCLK output. In other words, as N increases, the delay difference, P, between successive tap signals TN and TN+1reaches a point where it becomes smaller than the magnitude of the uncertainty in the edges of the MCLK output signal. The jitter in the MCLK clock signal arises from a variety of factors including slight differences in the inherent switching delay of individual gates 14, the cumulative effects of stochastic noise (xe2x80x9cshot noisexe2x80x9d) on the terminals of the gates 14 and natural oscillations in the feedback loop provided by controller 18. These factors can not be readily eliminated from the type of components forming clock signal generator 10. Also the resolution P of clock signal generator 10 can be no smaller than the minimum switching time of gates 14.
Thus we cannot increase the period resolution of the clock signal generator 10 by increasing the number N of gates 14 beyond that point at which the resolution becomes larger than the jitter or noise on MCLK or smaller than the minimum possible gate switching time. Unfortunately, many potentially useful applications for delay line based clock signal generators require higher clock period resolutions. What is needed is a delay line based clock signal generator with a higher effective period resolution.
A programmable clock signal generator adjusts timing of successive pulses of its output clock signal with a resolution of P seconds, where P is a constant. Thus edges of successive pulses of the clock signal are always separated by an interval of k*P seconds where k is an integer. In accordance with one aspect of the invention, the clock signal generator is programmed to produce a clock signal having an average period between successive pulses of j*P seconds, where j is a non-integer number by providing non-uniform intervals between successive clock signal pulses. For example, when the clock signal generator provides a clock signal having N pulse intervals of k for every one pulse interval of k+1, then the average interval between clock signal pulses is (N*k+1)P/(N+1). Note that the quantity (N*k+1)/(N+1) is not an integer for most combinations of integer values of N and k. While such a xe2x80x9cnon-uniform clock signalxe2x80x9d only approximates a xe2x80x9cuniform clock signalxe2x80x9d having uniform intervals of (N*k+1)P/(N+1) seconds between successive pulses, the non-uniform clock signal is nonetheless useful as a substitute for the uniform clock signal in applications that can tolerate small pulse timing errors.
For example, in accordance with another aspect of the invention a non-uniform clock signal is used in lieu of a uniform clock signal to control a rate at which a data sequence is supplied as input to a digital-to-analog converter (DAC). Although the analog signal produced by the DAC will be a somewhat distorted version of an analog signal the DAC would have produced had it been clocked by a uniform clock signal, the non-uniform clock signal will be an acceptable substitution for the uniform clock signal when the amount of analog signal distortion remains within an acceptable limit.
As another example, in accordance with a further aspect of the invention, such a non-uniform clock signal is used in lieu of a uniform clock signal to clock an analog-to-digital (A/D) converter for digitizing an analog signal at an average rate of (N*k+1)P/(N+1) seconds. Although the non-uniform clock signal""s pulse timing errors can cause errors in the digitizer""s output data, the non-uniform clock signal is a suitable substitute for the uniformly spaced clock signal when the data errors are within acceptable limits.
In applications where errors arising from use of such a non-uniform clock signal in lieu of a uniform clock signal are unacceptably large, the errors can be corrected. For example, a conventional Fourier transform algorithm can analyze the data output of the A/D converter to determine the frequency spectrum of the analog signal. However, errors in clock signal pulse timing will cause errors in frequency spectrum determination. If those errors are unacceptable, then in accordance with another aspect of the invention, the Fourier transform algorithm can be modified to compensate for the known, predictable clock signal pulse timing errors.
It is accordingly an object of the invention to provide a clock signal generator having a pulse timing resolution of P seconds which can nonetheless produce an output clock signal have an average period between pulses that is other than an integer multiple of P.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.